The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

May. 14, 2009
Applicants:

Sergey Sofer, Reshon Letzion, IL;

Yefim-haim Fefer, Petah-Tikva, IL;

Dov Tzytkin, Ness Zyiona, IL;

Inventors:

Sergey Sofer, Reshon Letzion, IL;

Yefim-Haim Fefer, Petah-Tikva, IL;

Dov Tzytkin, Ness Zyiona, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit, comprises a power supply node being connectable to a voltage supply (Vdd); a ground node connectable to ground (GND); and an electrostatic discharge protection structure for diverting an electrostatic discharge away from protected parts of the integrated circuit. A gated domain is present which is supply gated and/or ground gated with respect to the power supply node and/or the ground node, as well as a gating switch for gating the gated domain relative to the power supply node and/or the ground node. The gating switch enables in a connecting state, and in a disconnecting state inhibits, an electrical connection between the gated domain and at least one of: the power supply node and the ground node. The integrated circuit includes ESD gating control circuitry for controlling in case of an electrostatic discharge event the gated domain to be electrically connected to the power supply node and/or the ground node.


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