The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

Jul. 06, 2011
Applicants:

Daniel W. Bailey, Austin, TX (US);

Aaron S. Rogers, Pflugerville, TX (US);

James J. Montanaro, Austin, TX (US);

Bradley G. Burgess, Austin, TX (US);

Peter J. Hannan, Austin, TX (US);

Inventors:

Daniel W. Bailey, Austin, TX (US);

Aaron S. Rogers, Pflugerville, TX (US);

James J. Montanaro, Austin, TX (US);

Bradley G. Burgess, Austin, TX (US);

Peter J. Hannan, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
Abstract

Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.


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