The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Mar. 16, 2012
Gerald K. Bartley, Rochester, MN (US);
Russell Dean Hoover, Rochester, MN (US);
Charles Luther Johnson, Rochester, MN (US);
Steven Paul Vanderwiel, Rosemount, MN (US);
Gerald K. Bartley, Rochester, MN (US);
Russell Dean Hoover, Rochester, MN (US);
Charles Luther Johnson, Rochester, MN (US);
Steven Paul VanderWiel, Rosemount, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.