The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

Aug. 16, 2012
Applicants:

Yusuke Shimizu, Kyoto, JP;

Kenichi Shimomura, Hyogo, JP;

Inventors:

Yusuke Shimizu, Kyoto, JP;

Kenichi Shimomura, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01J 40/14 (2006.01); H04N 5/335 (2011.01); H03M 1/34 (2006.01); H04N 5/378 (2011.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H04N 5/37455 (2013.01);
Abstract

A solid-state imaging device includes: a column comparison circuit which compares a pixel signal with ramp waves and detects a timing at which the pixel signal and the ramp waves match; a counter circuit which is disposed for each of the pixel columns and measures the timing in the column comparison circuit by being supplied with a clock signal; and M first inverters which are equidistantly connected in series, wherein the counter circuit belongs to one of M groups corresponding to each of the M first inverters disposed in the upper clock stage, the odd-numbered group has second inverters disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group, and the even-numbered group has buffers disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group.


Find Patent Forward Citations

Shimizu, Yusuke. (2014). Solid-state imaging device comprising an analog to digital converter with column comparison circuits, column counter circuits, first and second inverters, and buffers (U.S. Patent No. 8735796). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8735796

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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