The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2014

Filed:

Sep. 28, 2011
Applicants:

Brett W. Coon, San Jose, CA (US);

John Erik Lindholm, Saratoga, CA (US);

Robert J. Stoll, Los Altos, CA (US);

Nicholas Wang, Saratoga, CA (US);

Jack Hilaire Choquette, Palo Alto, CA (US);

Kathleen Elliott Nickolls, Los Altos, CA (US);

Inventors:

Brett W. Coon, San Jose, CA (US);

John R. Nickolls, Los Altos, CA (US);

John Erik Lindholm, Saratoga, CA (US);

Robert J. Stoll, Los Altos, CA (US);

Nicholas Wang, Saratoga, CA (US);

Jack Hilaire Choquette, Palo Alto, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.


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