The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2014
Filed:
Aug. 02, 2012
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Eric Fluhr, Round Rock, TX (US);
Stephen G. Shuma, Underhill, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Michael H. Wood, Hopewell Junction, NY (US);
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Eric Fluhr, Round Rock, TX (US);
Stephen G. Shuma, Underhill, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Michael H. Wood, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.