Circuit and method with cache coherence stress control

Abstract

A circuit contains a shared memory (), that is used by a plurality of processing elements () that contain cache circuits () for caching data from the shared memory (). The processing elements perform a plurality of cooperating tasks, each task involving caching data from the shared memory () and sending cache message traffic. Consistency between cached data for different tasks is maintained by transmission of cache coherence requests via a communication network. Information from cache coherence requests generated for all of said tasks is buffered. One of the processing elements provides an indication signal indicating a current task stage of at least one of the processing elements. Additional cache message traffic is generated adapted dependent on the indication signal and the buffered information from the cache coherence requests. Thus conditions of cache traffic stress may be created to verify operability of the circuit, or cache message traffic may be delayed to avoid stress.