The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2014

Filed:

Mar. 29, 2013
Applicants:

Japan Display East, Inc., Chiba-ken, JP;

Panasonic Liquid Crystal Display Co., Ltd., Hyogo-ken, JP;

Inventors:

Masuyuki Ohta, Chiba-ken, JP;

Kazuhiro Ogawa, Chiba-ken, JP;

Keiichiro Ashizawa, Chiba-ken, JP;

Kazuhiko Yamagawa, Chiba-ken, JP;

Masahiro Yanai, Chiba-ken, JP;

Nobutake Konishi, Chiba-ken, JP;

Nobuyuki Suzuki, Chiba-ken, JP;

Masahiro Ishii, Chiba-ken, JP;

Makoto Yoneya, Ibaraki-ken, JP;

Sukekazu Aratani, Ibaraki-ken, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1343 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
Abstract

A liquid crystal display device includes first and second substrates with a liquid crystal layer disposed therebetween, a display region and a peripheral region, a gate signal line and an image signal line, an insulating layer formed over the gate signal line and the image signal line, a pixel electrode formed in the display region, a counter electrode formed over the insulating layer and formed by a first transparent conductive layer, and a second transparent conductive layer and an external connection terminal. The second transparent conductive layer and the external connection terminal are disposed in the peripheral region, and the second transparent conductive layer is formed over the insulating layer and is electrically connected to the counter electrode and the external connection terminal. A part of the gate signal line is covered by the second transparent conductive layer in the peripheral region.


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