The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2014

Filed:

Nov. 24, 2010
Applicants:

Carole D. Graas, Jericho, VT (US);

Keith A. Jenkins, Sleepy Hollow, NY (US);

Pascal A. Nsame, Essex Junction, VT (US);

Kevin G. Stawiasz, Bethel, CT (US);

Inventors:

Carole D. Graas, Jericho, VT (US);

Keith A. Jenkins, Sleepy Hollow, NY (US);

Pascal A. Nsame, Essex Junction, VT (US);

Kevin G. Stawiasz, Bethel, CT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01);
U.S. Cl.
CPC ...
Abstract

Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product.


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