The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2014

Filed:

Jun. 12, 2008
Applicants:

Christopher A. Vick, San Jose, CA (US);

Gregory M. Wright, Mountain View, CA (US);

Inventors:

Christopher A. Vick, San Jose, CA (US);

Gregory M. Wright, Mountain View, CA (US);

Assignee:

Oracle America, Inc., Redwood Shores, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 9/455 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 8/52 (2013.01); G06F 8/441 (2013.01); G06F 8/40 (2013.01); G06F 8/447 (2013.01); G06F 9/4552 (2013.01); G06F 12/00 (2013.01);
Abstract

One embodiment of the present invention provides a system that improves program performance by enregistering memory locations. During operation, the system receives program object code which has been generated to use a specified number of registers that are available for a given target hardware implementation. Next, the system translates this object code to execute on a second hardware implementation which includes more registers than the first hardware implementation. The system uses these additional registers to improve the performance of the translated object code for the second hardware implementation. More specifically, the system identifies a memory access in the object code, and then rewrites an instruction associated with this memory access to access an available register instead of the original target memory location. To preserve program semantics, the system subsequently moderates accesses to the memory location to ensure that no threads access a stale value in the enregistered memory location.


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