The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2014

Filed:

Jan. 21, 2009
Applicants:

Nigel C Paver, Austin, TX (US);

Stuart D Biles, Green Gincer, GB;

Kevin P Welton, Austin, TX (US);

Paul G Meyer, Bee Cave, TX (US);

Inventors:

Nigel C Paver, Austin, TX (US);

Stuart D Biles, Green Gincer, GB;

Kevin P Welton, Austin, TX (US);

Paul G Meyer, Bee Cave, TX (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0888 (2013.01); G06F 12/0891 (2013.01);
Abstract

A data processing system including a plurality of processorseach having a local cache memoryis provided. A cache coherency controllerserves to maintain cache coherency between the local cache memories. When one of the processorsis placed into a low power state its associated local cache memoryis maintained in a state in which the data it is holding is accessible to the cache coherency controlleruntil a predetermined condition has been met whereupon the local cache memoryconcerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.


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