Method and apparatus for adaptive voltage scaling based on instruction usage

Abstract

Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.