Buried power grid designs for improved radiation hardness in cmos technologies

Abstract

Buried power grids are designed as a fine mesh-type pattern of heavily doped diffusion regions with neutral epitaxial region cores to allow the uninterrupted electrical continuity of the epitaxial substrate, thus avoiding floating substrate effects. The buried power grids are formed beneath the epitaxial substrate surface and are powered via electrical contact to adjacent well regions. The buried power grids, when powered, form strongly reverse-biased buried pn junction regions that restrict radiation induced excess charge collection volumes and draw excess charge away from sensitive circuit nodes The method for forming buried power grids requires no uniquely complex process steps and no critical mask alignments to the CMOS devices on the epitaxial top surface. Buried power grids provide enhanced protection to sensitive circuit nodes against logic upsets due to single-particle and prompt dose radiation events and thereby improve the radiation hardness and decreases the latchup susceptibility of CMOS circuits.