The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2014
Filed:
Aug. 23, 2012
Hyung Sup Yoon, Daejeon, KR;
Byoung-gue Min, Daejeon, KR;
Jong Min Lee, Daejeon, KR;
Seong-il Kim, Daejeon, KR;
Dong Min Kang, Daejeon, KR;
Ho Kyun Ahn, Daejeon, KR;
Jong-won Lim, Daejeon, KR;
Jae Kyoung Mun, Daejeon, KR;
Eun Soo Nam, Daejeon, KR;
Hyung Sup Yoon, Daejeon, KR;
Byoung-Gue Min, Daejeon, KR;
Jong Min Lee, Daejeon, KR;
Seong-Il Kim, Daejeon, KR;
Dong Min Kang, Daejeon, KR;
Ho Kyun Ahn, Daejeon, KR;
Jong-Won Lim, Daejeon, KR;
Jae Kyoung Mun, Daejeon, KR;
Eun Soo Nam, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.