The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2014

Filed:

Aug. 20, 2012
Applicant:

Mitsumasa Koyanagi, Miyagi, JP;

Inventor:

Mitsumasa Koyanagi, Miyagi, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portionsof semiconductor chipsare temporarily adhered to corresponding temporary adhesion regionsof a carrier substrateby way of sticky material. The carrier substrateis then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portionsof the chipson the carrier substratewith corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portionsto the predetermined positions, the chipsare attached to the support substrate or the circuit layer with a desired layout.


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