The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2014
Filed:
Jun. 24, 2011
Zhitang Song, Shanghai, CN;
Liangcai Wu, Shanghai, CN;
Songlin Feng, Shanghai, CN;
Chinese Academy of Sciences, Shanghai, CN;
Abstract
The present invention discloses a phase change memory structure having low-k dielectric heat-insulating material and fabrication method thereof, wherein the phase change memory cell comprises diode, heating electrode, reversible phase change resistor, top electrode and etc; the heating electrode and reversible phase change resistor are surrounded by low-k dielectric heat-insulating layer; an anti-diffusion dielectric layer is designed between the reversible phase change resistor and the low-k dielectric heat-insulating layer surrounding thereof. The present invention utilizes low-k dielectric material as heat-insulating material, thereby avoiding thermal crosstalk and mutual influence during operation between phase change memory cells, enhancing the reliability of devices, and eliminating the influence of temperature, pressure and etc. on phase change random access memory (PCRAM) data retention during the change from amorphous to polycrystalline states. Furthermore, an anti-diffusion dielectric layer is prepared between the low-k dielectric material and the phase change material, which can be used to prevent the elements of the phase change material from diffusing to low-k dielectric material. The fabrication process of said phase change memory is compatible with standard complementary metal-oxide semiconductor (CMOS) process and the chemical mechanical polishing (CMP) process with low pressure and light corrosion is adopted in polishing.