The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2014
Filed:
Feb. 10, 2010
Applicants:
Francis Man-chit Chow, San Jose, CA (US);
Rakesh H. Patel, Cupertino, CA (US);
Erhard Joachim Pistorius, Mountain View, CA (US);
Inventors:
Francis Man-Chit Chow, San Jose, CA (US);
Rakesh H. Patel, Cupertino, CA (US);
Erhard Joachim Pistorius, Mountain View, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.