The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2014

Filed:

Sep. 22, 2009
Applicants:

Jie Xiao, Shenzhen, CN;

Bian Wu, Shenzhen, CN;

Fengbo Wu, Shenzhen, CN;

Chen Yu, Shenzhen, CN;

Inventors:

Jie Xiao, Shenzhen, CN;

Bian Wu, Shenzhen, CN;

Fengbo Wu, Shenzhen, CN;

Chen Yu, Shenzhen, CN;

Assignee:

ZTE Corporation, Shenzhen, Guangdong Province, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01); H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
H04L 47/215 (2013.01);
Abstract

A method and an apparatus for calculating packet arrival time interval are provided by the present invention. In the above-mentioned method, when the current packet arrives, system current time Tis read from a timer, and the arrival time T, recorded in an external RAM, of previous packet of the flow to which the current packet belongs is read (), wherein the timer implements a cycle timing with a period of preset time period T, the preset time period Tis larger than or equal to the time for filling the maximum depth of the token bucket of the flow at the minimum token injection rate; a current flag bit, recorded in an internal RAM, of the flow to which the current packet belongs is read (), wherein the current flag bit is used for indicating the number of cycles of the timer between the system current time Tand the arrival time Tof previous packet; and the arrival time interval of the present packet is calculated according to the system current time T, the arrival time Tof previous packet and the current flag bit (). Application of the present invention can reduce the consumption of the internal RAM and improve the operability for realizing by the hardware chips.


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