The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2014

Filed:

Nov. 29, 2010
Applicants:

Toshimitsu Tatsuka, Osaka, JP;

Hiromu Hasegawa, Osaka, JP;

Takeaki Komuro, Osaka, JP;

Masato Yamada, Osaka, JP;

Inventors:

Toshimitsu Tatsuka, Osaka, JP;

Hiromu Hasegawa, Osaka, JP;

Takeaki Komuro, Osaka, JP;

Masato Yamada, Osaka, JP;

Assignee:

MegaChips Corporation, Osaka-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame. The controller includes a first processing unit that obtains a generated amount of code used for a first predetermined number of immediately preceding macroblocks, a second processing unit that obtains an allowable amount of code available for a third predetermined number of immediately subsequent macroblocks including a currently target macroblock, based on a target amount of code for not more than a second predetermined number of macroblocks less than a total number of macroblocks included in one frame, and the generated amount of code obtained by the first processing unit, a third processing unit that obtains an expected amount of code expected to be used for the third predetermined number of macroblocks, and a fourth processing unit that sets a quantization parameter of a currently target macroblock, based on the allowable amount of code obtained by the second processing unit and the expected amount of code obtained by the third processing unit.


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