The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2014

Filed:

Feb. 03, 2011
Applicants:

Ravindraraj Ramaraju, Round Rock, TX (US);

David R. Bearden, Austin, TX (US);

Andrew C. Russell, Austin, TX (US);

Shayan Zhang, Austin, TX (US);

Inventors:

Ravindraraj Ramaraju, Round Rock, TX (US);

David R. Bearden, Austin, TX (US);

Andrew C. Russell, Austin, TX (US);

Shayan Zhang, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); G05F 3/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.


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