The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2014
Filed:
Mar. 13, 2012
Jong-cheol Lee, Seoul, KR;
Jun-noh Lee, Gyeonggi-do, KR;
Ki-vin Im, Gyeonggi-do, KR;
Ki-yeon Park, Seoul, KR;
Sung-hae Lee, Gyeonggi-do, KR;
Sang-yeol Kang, Gyeonggi-do, KR;
Jong-cheol Lee, Seoul, KR;
Jun-noh Lee, Gyeonggi-do, KR;
Ki-vin Im, Gyeonggi-do, KR;
Ki-yeon Park, Seoul, KR;
Sung-hae Lee, Gyeonggi-do, KR;
Sang-yeol Kang, Gyeonggi-do, KR;
Abstract
Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.