The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2014
Filed:
Jun. 29, 2012
Nobuhiro Tsuda, Tokyo, JP;
Hidekatsu Nishimaki, Tokyo, JP;
Hiroshi Omura, Tokyo, JP;
Yuko Yoshifuku, Tokyo, JP;
Nobuhiro Tsuda, Tokyo, JP;
Hidekatsu Nishimaki, Tokyo, JP;
Hiroshi Omura, Tokyo, JP;
Yuko Yoshifuku, Tokyo, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.