Implementing state-of-the-art gate transistor, sidewall profile/angle control by tuning gate etch process recipe parameters

Abstract

In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.