Simple circular asynchronous clock domain crossing technique for digital data

Abstract

A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may be used to pass data between the two clock domains. In one embodiment, a set of storage devices is connected in a circular buffer arrangement. A first subset of the storage devices is clocked by a signal from a first clock domain and a second subset of the flip flops is clocked by a signal taken from a second clock domain. Respective output circuits generate enable signals to be used for transferring data between domains. In some implementations, a pulse is stored and registered by at least two of the storage devices in the first domain before being passed to the devices in the second domain. In other embodiments, the output circuits may include a pair of D flip flops, each clocked by a respective one of the first or second domain signals. In specific arrangements, an output flip flop takes its data input from a logical AND of signals output from a flip flop within its associated domain, to ensure that the enable signal is asserted for only a single output clock cycle, and/or a second flip flop uses a logical AND of its input and inverted output states to avoid metastable conditions.