The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2014

Filed:

Aug. 11, 2009
Applicants:

Heinrich Schemmann, Villingen-Schwenningen, DE;

Petrus Gijsbertus Maria Centen, Goirle, NL;

Sabine Roth, Moenchweiler, DE;

Boon Keng Teng, Singapore, SG;

Inventors:

Heinrich Schemmann, Villingen-Schwenningen, DE;

Petrus Gijsbertus Maria Centen, Goirle, NL;

Sabine Roth, Moenchweiler, DE;

Boon Keng Teng, Singapore, SG;

Assignee:

Thomson Licensing, Issy-les-Moulineaux, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CMOS image sensor allows for selectively outputting one of two vertical resolutions, e.g. 1080 to 720 lines. The scan conversion is implemented completely on the image sensor chip by using smaller sub-pixel cores, which can be electrically combined via switch transistors. A basic circuit of the CMOS image sensor has a number of pixel cells arranged in lines and columns. Each pixel cell has a photosensitive element that converts impinging light into electric charge and a first transfer element. The first transfer elements of m pixel cells arranged consecutively in the same column are arranged for transferring the charge generated in the respective m photosensitive elements during exposure to a single first charge storage element provided for the respective group of m pixel cells. In an exemplary embodiment the switching scheme allows for combining the signal information of either two or three vertically adjacent sub-pixel cores.


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