The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2014
Filed:
Jun. 26, 2009
Jeevak M. Parpia, Ithaca, NY (US);
Harold G. Craighead, Ithaca, NY (US);
Joshua D. Cross, Ithaca, NY (US);
Bojan Robert Ilic, Ithaca, NY (US);
Maxim K. Zalalutdinov, Silver Spring, MD (US);
Jeffrey W. Baldwin, Alexandria, VA (US);
Brian H. Houston, Fairfax, VA (US);
Jeevak M. Parpia, Ithaca, NY (US);
Harold G. Craighead, Ithaca, NY (US);
Joshua D. Cross, Ithaca, NY (US);
Bojan Robert Ilic, Ithaca, NY (US);
Maxim K. Zalalutdinov, Silver Spring, MD (US);
Jeffrey W. Baldwin, Alexandria, VA (US);
Brian H. Houston, Fairfax, VA (US);
Cornell University, Ithaca, NY (US);
Abstract
The present invention is directed to a CMOS integrated micromechanical device fabricated in accordance with a standard CMOS foundry fabrication process. The standard CMOS foundry fabrication process is characterized by a predetermined layer map and a predetermined set of fabrication rules. The device includes a semiconductor substrate formed or provided in accordance with the predetermined layer map and the predetermined set of fabrication rules. A MEMS resonator device is fabricated in accordance with the predetermined layer map and the predetermined set of fabrication rules. The MEMS resonator device includes a micromechanical resonator structure having a surface area greater than or equal to approximately 20 square microns. At least one CMOS circuit is coupled to the MEMS resonator member. The at least one CMOS circuit is also fabricated in accordance with the predetermined layer map and the predetermined set of fabrication rules.