Interference mitigation in mixed signal integrated circuits (ics)

Abstract

A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.