The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
Feb. 27, 2013
Fujitsu Limited, Kawasaki, JP;
Kazumasa Kubotera, Kawasaki, JP;
Yasutaka Kanayama, Inagi, JP;
Masaki Fujioka, Yokohama, JP;
Hiroshi Miyake, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Fujitsu Semiconductor Limited, Yokohama, JP;
Abstract
Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is '0', and outputs a signal input to a first input terminal when the set signal is '1', and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile