Gigabit-speed slicer latch with hysteresis optimization

Abstract

Improved master latch for high-speed slicer providing enhanced input signal sensitivity. A pre-charging circuit injects charge into the sources of the differential pair of a latch that samples the input signal during odd clock cycles. This reduces the gate-to-source voltage of the sampling pair, making them less sensitive to data bits latched by a second parallel master latch in odd clock cycles. The injected charge dissipates before the sampling pair is needed to fully sample the input signal in even clock cycles. The pre-charging circuit includes a current mirror, a current source and a transistor that couples the current source to the current mirror during odd clock cycles. A shunt peaked amplifier with excess peaking boosts the high-frequency content of a differential input signal relative to its low-frequency content. Capacitors cross-couple the gates and drains of the differential sampling pair. These supply an equal but opposite gate current than supplied by the intrinsic gate-to-drain capacitance, thereby reducing net current to the gate, and jitter on the input signal.