The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 2014

Filed:

Aug. 19, 2011
Applicants:

Irfan Rahim, Milpitas, CA (US);

Jeffrey T. Watt, Palo Alto, CA (US);

Richard G. Cliff, Los Altos, CA (US);

Andy L. Lee, San Jose, CA (US);

Ping-chen Liu, Fremont, CA (US);

Inventors:

Irfan Rahim, Milpitas, CA (US);

Jeffrey T. Watt, Palo Alto, CA (US);

Richard G. Cliff, Los Altos, CA (US);

Andy L. Lee, San Jose, CA (US);

Ping-Chen Liu, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.


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