The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
May. 24, 2010
Naoto Taoka, Tokyo, JP;
Atsushi Nakamura, Tokyo, JP;
Naozumi Morino, Tokyo, JP;
Toshikazu Ishikawa, Tokyo, JP;
Nobuhiro Kinoshita, Tokyo, JP;
Naoto Taoka, Tokyo, JP;
Atsushi Nakamura, Tokyo, JP;
Naozumi Morino, Tokyo, JP;
Toshikazu Ishikawa, Tokyo, JP;
Nobuhiro Kinoshita, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).