The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
Jan. 11, 2011
Jae Kyoung Mun, Daejeon, KR;
Hong Gu Ji, Daejeon, KR;
Ho Kyun Ahn, Daejeon, KR;
Hae Cheon Kim, Daejeon, KR;
Jae Kyoung Mun, Daejeon, KR;
Hong Gu Ji, Daejeon, KR;
Ho Kyun Ahn, Daejeon, KR;
Hae Cheon Kim, Daejeon, KR;
Abstract
Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.