The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 2014

Filed:

Mar. 13, 2012
Applicants:

Vinayak Tilak, Niskayuna, NY (US);

Alexei Vertiatchikh, Schenectady, NY (US);

Kevin Sean Matocha, Rexford, NY (US);

Peter Micah Sandvik, Clifton Park, NY (US);

Siddharth Rajan, Goleta, CA (US);

Inventors:

Vinayak Tilak, Niskayuna, NY (US);

Alexei Vertiatchikh, Schenectady, NY (US);

Kevin Sean Matocha, Rexford, NY (US);

Peter Micah Sandvik, Clifton Park, NY (US);

Siddharth Rajan, Goleta, CA (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/335 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.


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