The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2014

Filed:

Dec. 21, 2009
Applicants:

Sze Huey Soo, Gurun, MY;

Thow Pang Chong, Sungai Ara, MY;

Boon Jin Ang, Bagan Ajam Butterworth, MY;

Kar Keng Chua, Juru, MY;

Inventors:

Sze Huey Soo, Gurun, MY;

Thow Pang Chong, Sungai Ara, MY;

Boon Jin Ang, Bagan Ajam Butterworth, MY;

Kar Keng Chua, Juru, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.


Find Patent Forward Citations

Loading…