The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2014

Filed:

Jul. 11, 2012
Applicants:

William R. Griesbach, Pocono Lake, PA (US);

Clayton E. Schneider, Jr., Bethlehem, PA (US);

Inventors:

William R. Griesbach, Pocono Lake, PA (US);

Clayton E. Schneider, Jr., Bethlehem, PA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: () a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and () an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters.


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