Phase-locked loop based clock generator and method for operating same

Abstract

An integer-N phase-locked loop based clock generator for generating an output clock signal with a frequency N multiples of a reference clock signal, and a method for same, wherein N is a positive integer. The integer-N clock phase-locked loop based generator comprises a reference clock, a voltage controlled oscillator, a clock divider, a first and second phase generator for generating a plurality of phases of the reference clock signal and divided down output clock signal, a plurality of phase frequency detectors and charge pumps. The method comprises generating a reference clock and an output clock signals, generating a plurality of phases of a divided down output clock signal and reference clock signal, comparing the plurality of phases, and changing the frequency of the output clock signal based on the comparison.