The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Aug. 11, 2011
Edgar R. Cordero, Round Rock, TX (US);
Divya Kumar, Austin, TX (US);
Anuwat Saetow, Austin, TX (US);
Robert B. Tremaine, Stormville, NY (US);
Edgar R. Cordero, Round Rock, TX (US);
Divya Kumar, Austin, TX (US);
Anuwat Saetow, Austin, TX (US);
Robert B. Tremaine, Stormville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.