The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Nov. 12, 2008
Ming-hsien Lee, Kaohsiung, TW;
Ching-chieh Shih, Kinmen County, TW;
An-thung Cho, Hualien County, TW;
Chia-tien Peng, Hsinchu County, TW;
Kun-chih Lin, Miaoli County, TW;
Ming-Hsien Lee, Kaohsiung, TW;
Ching-Chieh Shih, Kinmen County, TW;
An-Thung Cho, Hualien County, TW;
Chia-Tien Peng, Hsinchu County, TW;
Kun-Chih Lin, Miaoli County, TW;
Au Optronics Corporation, Hsinchu, TW;
Abstract
A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.