Memory devices containing a high-k dielectric layer

Abstract

In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO.