The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2014

Filed:

Mar. 14, 2013
Applicant:

Dongbu Hitek Co., Ltd., Gyeonggi-do, KR;

Inventors:

Seong Hun Jeong, Gyeonggi-do, KR;

Ki Jun Yun, Gyeonggi-do, KR;

Oh Jin Jung, Gyeonggi-do, KR;

Assignee:

Dongbu HiTek Co., Ltd., Bucheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/4763 (2006.01); H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); G01P 15/135 (2006.01); H01H 35/02 (2006.01); H01H 35/14 (2006.01); G01P 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device including at least one of the following steps: () Forming a plurality of lower electrodes over a substrate. () Forming a first stop film over the lower electrodes. () Forming a filling layer over the first stop film. () Forming a second stop film over the filling layer. () Forming a first interlayer insulating layer over the second stop film. () Forming a plurality of upper electrodes over the first interlayer insulating layer. () Forming a second interlayer insulating layer over the upper electrodes. () Etching the second interlayer insulating layer and the first interlayer insulating layer to form a cavity. () Forming a contact ball in the cavity.


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