The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2014

Filed:

Nov. 04, 2005
Applicants:

Ashish Karandikar, Sunnyvale, CA (US);

Shirish Gadre, Fremont, CA (US);

Stephen D. Lew, Sunnyvale, CA (US);

Inventors:

Ashish Karandikar, Sunnyvale, CA (US);

Shirish Gadre, Fremont, CA (US);

Stephen D. Lew, Sunnyvale, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/16 (2006.01); G06F 15/80 (2006.01); G06F 13/14 (2006.01); G09G 5/39 (2006.01); G09G 5/36 (2006.01); G06F 7/32 (2006.01); G06F 13/00 (2006.01); G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.


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