The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
May. 31, 2012
Emmanouil Frantzeskakis, Ilioupolis, GR;
Ioannis L. Syllaios, Costa Mesa, CA (US);
Georgios Sfikas, Glyfada, GR;
Henrik Jensen, Long Beach, CA (US);
Stephen Wu, Fountain Valley, CA (US);
Padmanava Sen, Irvine, CA (US);
Emmanouil Frantzeskakis, Ilioupolis, GR;
Ioannis L. Syllaios, Costa Mesa, CA (US);
Georgios Sfikas, Glyfada, GR;
Henrik Jensen, Long Beach, CA (US);
Stephen Wu, Fountain Valley, CA (US);
Padmanava Sen, Irvine, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile