Apparatus and method for a programmable timing in peak current mode controlled power converters

Abstract

An apparatus and a method for a programmable timing in digital integrated circuits implementing peak current mode controlled power converters are disclosed. The programmable dead-time is implemented by means implemented in hardware, software, and combination of hardware and software, carrying out setting a second timer value; setting a third timer value with respect to the second timer value; detecting a reset event; reloading a second counter from a current timer value to the second timer value upon detecting the reset event; resetting a second pulse width modulated waveform amplitude from a second amplitude value to a first amplitude value upon detecting the reset event; and setting a first pulse width modulated waveform from a first amplitude value to a second value upon the second counter reaching a third value.