The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Sep. 30, 2011
Applicant:
Anatoly Gelman, San Diego, CA (US);
Inventor:
Anatoly Gelman, San Diego, CA (US);
Assignee:
Broadcom Corporation, Irvine, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Methods, systems, and computer program products are provided to implement clock gating with double data rate ('DDR') logic. In traditional single data rate ('SDR') clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking.