The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Mar. 14, 2013
Palo Alto Research Center Incorporated, Palo Alto, CA (US);
Eugene M. Chow, Fremont, CA (US);
Dirk DeBruyker, San Jose, CA (US);
Palo Alto Research Center Incorporated, Palo Alto, CA (US);
Abstract
A stacked-die electronic package assembly includes IC chips connected to a base substrate in a flip-chip, offset (e.g., pyramid-type) stacked arrangement by way of single-curved interconnect springs. Each interconnect spring is patterned from a spring metal film that bends to form a cantilevered structure having an anchor portion secured to the base substrate, a body portion that curves upward from the base substrate, and a tip disposed at the free end of the body portion. The IC chips are mounted onto interconnect springs such that contact pads on the chips contact the spring tips, causing the springs to slightly compress. Optional solder is utilized to secure the connection of the spring tips to the contact pads. Optional spacers and adhesive are utilized to maintain proper spacing between the IC chips and the base substrate. The springs are formed with different tip heights to facilitate connection to the stacked IC chips.