The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Sep. 05, 2012
Sung-ryul Kim, Cheonan-si, KR;
Jean-ho Song, Seoul, KR;
Jae-hyoung Youn, Seoul, KR;
O-sung Seo, Seoul, KR;
Byeong-beom Kim, Suwon-si, KR;
Je-hyeong Park, Hwaseong-si, KR;
Jong-in Kim, Suwon-si, KR;
Jae-jin Song, Hwaseong-si, KR;
Sung-Ryul Kim, Cheonan-si, KR;
Jean-Ho Song, Seoul, KR;
Jae-Hyoung Youn, Seoul, KR;
O-Sung Seo, Seoul, KR;
Byeong-Beom Kim, Suwon-si, KR;
Je-Hyeong Park, Hwaseong-si, KR;
Jong-In Kim, Suwon-si, KR;
Jae-Jin Song, Hwaseong-si, KR;
Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;
Abstract
A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.