The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Oct. 27, 2010
Amlan Majumdar, White Plains, NY (US);
Robert J. Miller, Yorktown Heights, NY (US);
Muralidhar Ramachandran, Mahopac, NY (US);
Amlan Majumdar, White Plains, NY (US);
Robert J. Miller, Yorktown Heights, NY (US);
Muralidhar Ramachandran, Mahopac, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices Corporation, Sunnyvale, CA (US);
Freescale Semiconductor Corporation, Austin, TX (US);
Abstract
A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.