The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Feb. 17, 2011
Gary Chorng-jyh Wang, Cupertino, CA (US);
Ching Yen Ho, Los Gatos, CA (US);
Wen Jang Hwang, Fremont, CA (US);
Wilson Wen-fu Wang, San Jose, CA (US);
Gary Chorng-Jyh Wang, Cupertino, CA (US);
Ching Yen Ho, Los Gatos, CA (US);
Wen Jang Hwang, Fremont, CA (US);
Wilson Wen-Fu Wang, San Jose, CA (US);
Sparkle Power Inc., San Jose, CA (US);
Abstract
The system relates to filed-programmable lab-on-chip (FPLOC) microfluidic operations, fabrications, and programming based on Microelectrode Array Architecture are disclosed herein. The FPLOC device by employing the microelectrode array architecture may include the following: (a) a bottom plate comprising an array of multiple microelectrodes disposed on a top surface of a substrate covered by a dielectric layer; wherein each of the microelectrode is coupled to at least one grounding elements of a grounding mechanism, wherein a hydrophobic layer is disposed on the top of the dielectric layer and the grounding elements to make hydrophobic surfaces with the droplets; (b) a field programmability mechanism for programming a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes; and, (c) a FPLOC functional block, comprising: (i) I/O ports; (ii) a sample preparation unit; (iii) a droplet manipulation unit; (iv) a detection unit; and (iv) a system control unit.