The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Oct. 27, 2010
John F. Bulzacchelli, Yonkers, NY (US);
Timothy O. Dickson, Danbury, CT (US);
Frank D. Ferraiolo, Essex Junction, VT (US);
Robert J. Reese, Austin, TX (US);
Michael B. Spear, Round Rock, TX (US);
John F. Bulzacchelli, Yonkers, NY (US);
Timothy O. Dickson, Danbury, CT (US);
Frank D. Ferraiolo, Essex Junction, VT (US);
Robert J. Reese, Austin, TX (US);
Michael B. Spear, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.