The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2014

Filed:

Apr. 30, 2010
Applicants:

Richard J. Carter, Los Altos, CA (US);

Muhammad Shakeel Qureshi, Santa Clara, CA (US);

Inventors:

Richard J. Carter, Los Altos, CA (US);

Muhammad Shakeel Qureshi, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable current-limited voltage buffer. The programmable current-limited voltage buffer includes at least one current-bias circuit, an inverter, a write-current set control circuit, and an adaptive current limiter. The inverter is coupled to the current-bias circuit and a reference-voltage source, and is configured to couple a row line to either the current-bias circuit, or the reference-voltage source, in response to an input signal. The adaptive current limiter is coupled to the current-bias circuit and to the write-current set control circuit, and is configured to limit current flowing through the memory element in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element during switching in an array of memory elements.


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